1. Field of the Invention
The present invention relates to a method for fabricating a non-volatile semiconductor memory device, and more particularly to a method for fabricating a non-volatile semiconductor memory device having a two-layered gate electrode transistor.
2. Description of the Related Art
A typical example of a conventional non-volatile semiconductor memory device is shown in FIG. 1 and its fabrication steps are illustrated in FIGS. 2A through 7A and 2B through 7B. First, a conventional method for fabricating the semiconductor memory device is explained with reference to the drawings. FIGS. 2A through 7A are sectional views of the device taken along the line A--A' in FIG. 1 and FIGS. 2B through 7B are sectional views of the same device taken along the line B--B' in FIG. 1 for explaining each of the sequential fabrication steps.
The arrangement shown in FIG. 1 includes a drain region 200, a source region 201, a channel region 202, a control gate electrode 203, a floating gate electrode 204, a drain contact hole 205, a metal wiring 206 and an element isolation region 207.
First, on a predetermined region of a semiconductor substrate 1 made of a material such as silicon (Si) are formed a first insulating film 2 and a first gate insulating film 4 made of such as silicon dioxide (SiO.sub.2) by a conventional method. Next, after a first polycrystalline silicon film 5 is patterned at predetermined regions, a second gate insulating film 6 made of such as silicon dioxide is formed (FIGS. 2A and 2B).
Next, a second polycrystalline silicon film 7 is formed (FIGS. 3A and 3B). Then, a patterning mask 15 of such as a resist is formed so as to cover only the portion which becomes a control gate electrode. With this mask being used, the second polycrystalline silicon film 7, the second gate insulating film 6, and the first polycrystalline silicon film 5 are sequentially and selectively etched. For conducting these etchings, the most common technique used is, for purposes of reducing size deviations, anisotropic etching such as reactive ion etching (RIE) (FIGS. 4A and 4B).
Thereafter, the first gate insulating film 4 that is exposed is etched-back and, after the patterning mask 15 is removed, a second insulating film 34 of such as silicon dioxide is formed. Then, implantation of N-type impurities of such as arsenic (As) is performed, thereby forming a drain region 22 and a source region 23. For example, a first interlayer insulating film 25 of TEOS (Tetraethylortho-silicate Si(OC.sub.2 H.sub.5).sub.4) or BPSG (Boro-phospho-silicate glass) is formed using a low pressure Chemical Vapor Deposition (CVD) method (FIGS. 5A and 5B).
Furthermore, a drain contact hole 27 and a source contact hole (not shown) are formed using, for example, a patterning mask 26 (FIGS. 6A and 6B).
After the patterning mask 26 is removed, a metal wiring 28 of, for example, aluminum (Al) is patterned, whereby a non-volatile semiconductor memory device shown in FIGS. 7A and 7B is obtained.
In the conventional method for fabricating a nonvolatile semiconductor memory device described above, the occurrence of bird's beaks cannot be avoided since element isolation regions are formed by oxidizing an upper part of the semiconductor substrate.
The bird's beaks not only cause the channel current to be reduced due to the reduction in the channel width but also make it difficult to scale down the element isolation regions. This is a great barrier for the enhancement of higher integration of the memory cells.
Also, in the conventional device, since the drain/source regions are provided on a semiconductor substrate, it is not possible to avoid a Junction leakage current to be generated when the voltage is applied. This presents a problem in that the current consumption is wasted where the device is highly integrated.